Semiconductor Engineering

GPUs May Speed UP EDA Algorithms

The sequential EDA algorithms of old cannot keep pace with increasing design complexity, which is driving the industry to look at parallelism and other computational architectures such as the ...
EDN

EDA startup promises algorithm-to-tapeout synthesis

SANTA CRUZ, Calif. — Leveraging technology from Hewlett-Packard Co.'s research labs, EDA startup Synfora Inc. this week will announce plans to offer “algorithm to tapeout” synthesis. The offering ...
Design-Reuse

Agilent Technologies' New Electronic System-Level EDA Platform Helps Algorithm Developers, System Architects Cut Design Time in Half

SANTA CLARA, Calif. -- Sept. 17, 2008-- Agilent Technologies Inc. (NYSE: A) today introduced SystemVue 2008, a new electronic design automation (EDA) platform for electronic system-level (ESL) design.
Electronics Weekly

C++ synthesis suite for PolarFire FPGA algorithm development

Microchip has released a C++ algorithm high-level synthesis design workflow for its PolarFire FPGAs. “A large majority of edge compute, computer vision and industrial control algorithms are developed ...