Nature

Low-Density Parity-Check Decoder Architectures and Algorithms

Low-Density Parity-Check (LDPC) decoder designs have undergone significant evolution, driven by the need for high-throughput, low-complexity and energy-efficient ...
EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
Nature

Non-Binary LDPC Code Decoding Algorithms

Non-binary low-density parity-check (LDPC) codes extend conventional binary LDPC schemes by operating over larger Galois fields, affording stronger error-correction ...
Design-Reuse

Unified C-programmable ASIP architecture for multi-standard Viterbi, Turbo and LDPC decoding

This paper describes an ASIP decoder template suitable for multi-standard Viterbi, Turbo and LDPC decoding. We show architecture fitness for WLAN, WiMAX and 3GPPLTE standards, although various other ...
Design-Reuse

DVB-T2 Demodulator + Decoder LDPC/ BCH IP Core Available For Immediate Implementation From Global IP Core

March 7, 2023 - Global IP Core Sales - The new DVB-T2 demodulator is designed to be used together with an RF tuner, and an analog to digital converter. The system has an internal state machine to ...
New Electronics

AccelerComm develops LDPC Decoder for Intel’s FlexRAN

AccelerComm, the company specialising in optimisation and latency reduction IP, has announced they have developed a highly optimised LDPC software decoder in collaboration with Intel. The solution is ...
EDN

LDPC: Another Key Step Toward Shannon

For communication designers, especially those in the networking and wireless field, the Shannon limit can be seen as the Holy Grail. And, since being first defined in ...